Imec Addresses 3-D ICs, Interconnects, Cryogenic Etching, and Solar Cells
July 14, 2013. Imec made several announcements at SEMICON West last week. The organization is collaborating with Dow Corning on 3-D IC packaging technologies, announced it developed a manganese (Mn)-based self-formed barrier (SFB) process that significantly improves interconnect resistance-capacitance (RC) performance, and described a cryogenic etching method that protects the surface of porous ultralow-k dielectrics. In addition, at co-located Intersolar, imomec (an imec-associated lab) and Solliance presented a thin-film solar cell with 9.7% efficiency.
Dow Corning, an innovator in silicones and silicon-based technology is among the newest member organizations to join imec. The announcement signals expanded opportunities for both organizations to combine their expertise toward the development and broader adoption of 3-D integrated circuit (IC) packaging technologies, wherein IC chips are stacked in vertical 3-D architectures.
“This move is a natural and strategic step for Dow Corning and imec, as we both believe collaborative innovation is as critical to industry leadership as native expertise,” said Andrew Ho, global industry director for advanced semiconductor materials at Dow Corning. “Our access to imec’s world-class resources and expertise will not only help us further refine our unique temporary bonding solution, it will allow imec to leverage that solution to advance integration of the 3D IC packaging process that they’ve been developing for years.”
By integrating multiple chips into a single package, 3-D IC technology promises to reduce form factor and power consumption and increase bandwidth to enable more efficient interchip communication for next-generation microelectronics devices. Yet, before 3-D IC fabrication can see broader adoption, it will require innovative advances in materials and processing technologies.
One of the key challenges imec is tackling is the bonding of the device wafer to a carrier wafer, prior to wafer thinning, and the safe debonding of the thin wafer after completion of backside processing. This was Dow Corning’s goal when designing its Temporary Bonding Solution, which aims at simple processing using a bi-layer concept comprising an adhesive and release layer. The technology also enables room-temperature bonding and debonding processes based on standard manufacturing methods.
Together with imec, Dow Corning will explore its temporary bonding CMOS-compatible solution for 3D Through-Silicon-Via (TSV) semiconductor packaging. The collaboration will aim to further expand the technology’s ability to achieve simple, cost-effective bonding-debonding techniques compatible with standard manufacturing processes.
“Imec’s precompetitive programs are an essential platform for industry leaders to share the risk and cost of advanced research. As one of the semiconductor industry’s most proven pioneers in advanced silicone-based solutions, Dow Corning brings valuable materials and processing expertise to imec’s global network of innovators—as well as a key enabling technology for TSV fabrication,” said Eric Beyne, program director, 3D System Integration, at imec. “We look forward to collaborating closely with our newest member organization as we drive the next stage of 3D integration, and help ensure compatiblity of the proposed thin-wafer carrier solution with advanced, sub-10-nanometer CMOS device technologies.”
Imec Solves Metallization Issues
Imec also said it has developed a manganese (Mn)-based self-formed barrier (SFB) process that significantly improves resistance-capacitance (RC) performance in advanced interconnects. Imec said the process provides excellent adhesion, film conformality, intrinsic barrier property, and reduced line resistance. This technology paves the way towards interconnect Cu metallization into the 7-nm node and beyond.
With continuous interconnect scaling, the wire resistance per unit length increases, which has a detrimental impact on the device performance (RC). Moreover, when reducing the dimensions with conventional barrier layers, an increased loss of copper (Cu) cross-sectional area is observed, resulting in high resistance and decreased interconnect lifetime (electro-migration and time dependent dielectric breakdown—EM and TDDB). To overcome these interconnect metallization issues when scaling beyond the 1X technology node, imec’s R&D program on advanced interconnect technology explores new barrier and seed materials as well as novel deposition and filling techniques. The Mn-based SFB was demonstrated to be an attractive candidate for future interconnect technology. At module level, Mn-based SFB resulted in a 40% increase in RC benefits at 40-nm half-pitch compared with conventional barrier and good lifetime performance (comparable to TaN/Ta reference).
These results were achieved in cooperation with imec’s key partners in its core CMOS programs: GLOBALFOUNDRIES, Intel, Micron, Panasonic, Samsung, TSMC, Elpida, SK Hynix, Fujitsu, and Sony.
Cryogenic Etching of Ultralow-K Dielectrics
Imec also announced a cryogenic etching method that protects the surface of porous ultralow-k dielectrics against excessive plasma induced damages.
As semiconductor technology scales below the 20-nm node, the capacitance increases between nearby conductive portions of high-density integrated circuits, resulting in loss of speed and cross-talk of the device. To control the increase in capacitance in deeply-scaled devices, insulating layers of porous low-k dielectrics are integrated through plasma etching. However, plasma etching exposes the dielectrics to active plasma radicals that penetrate deeply into the porous substrate, which then react and change the composition of the dielectric.
To bypass such damages, imec developed a new cryogenic etching method. By applying very low (cryogenic) temperatures during etching, a condensation of etch products in the pores of the low-k material, results in a protection of the dielectrics’ surface. Imec demonstrated the method on a porous organosilicate (OSG) film. The results showed that no carbon depletion occurred when the wafer temperature remained below a certain critical level during plasma etching.
“Our cryogenic etch method solves a key issue to further advancing scaling limits. It overcomes the disadvantages of current methods used to reduce plasma-induced damage, such as dielectric etch at regular temperatures or low-k repair or high-temperature pore stuffing, and it enables sub k=2.0 materials for integration,” stated Zsolt Tokei, program director, interconnect, at imec. “Our method is a true solution to further drive the development of next-generation, deeply-scaled technologies.”
Thin-Film CZTSe Solar Cell at Intersolar
And at Intersolar, co-llocated with SEMICON West, imomec, imec’s associated lab at Hasselt University, and Solliance, the European R&D consortium that focuses on thin-film photovoltaic solar energy (PV), presented a CZTSe (Cu2ZnSnSe4)-based solar cell with 9.7% efficiency. This promising result is an important step bringing the solar industry closer to a sustainable alternative for the highest efficiency thin-film solar cells in production, based on CIGS, or Cu(In,Ga)(S,Se)2.
CZTSe is an emerging alternative solar cell absorber in thin-film solar cells, similar to CZTS (Cu2ZnSnS4). Unlike CIGS, CZTS and CZTSe do not suffer from abundancy issues. At 1.5 to 1.6 eV for CZTS, and 0.9 eV for CZTSe, their bandgaps make a combined material system ideal for a multi-junction, thin-film solar cell that rivals the efficiency of CIGS cells (about 20%). Imomec, imec, and Solliance have defined a path towards further improving the layers and cell structures of CZTSe and CZTS absorbers aiming at developing a multi junction CZTS/CZTSe solar cell with 20% cell efficiency. The presented CZTSe solar cell is an important step forward to reach this goal.
Imec/imomec fabricated the CZTSe layers by sputtering Cu, Zn, and Sn metal layers on a molybdenum-on-glass substrate and subsequently annealing-in an H2Se-containing atmosphere, achieving 9.7% efficiency. The resulting polycrystalline absorber layers are only 1 µm thick, with a typical grain size of about 1 µm. The samples were then processed at Helmholtz Zentrum Berlin into solar cells using a standard process flow for thin-film solar cells and finished with a metal grid and anti-reflective coating at imec. The highest efficiency obtained on a 1x1-cm2 cell was 9.7%, with a maximum short-circuit current of 38.9 mA/cm2, an open-circuit voltage of 0.41 V, and a fill factor of 61%.
“This is a big win for us. We’ve been working toward this milestone since 2011 when we first started our research on alternative materials for thin-film photovoltaics at imec/imomec,” said Marc Meuris, program manager at Solliance of the alternative thin-film PV program. “Our efficiencies are the highest in Europe and approaching the world record for this type of thin-film solar cells, and we look forward to further advancing R&D to help bringing to market sustainable energy sources.”
The sputtering of the Cu, Zn, and Sn layers was performed at Flamac (Gent), and the international glass manufacturer AGC delivered molybdenum-on- glass substrates. Imec’s thin-film solar cell activities at imomec are integrated in the Solliance cross-border collaboration platform, and the research was partially supported by the Flemish Strategisch Initiatief Materialen (SIM) SoPPoM program.