LPC Microcontrollers Optimized for System Design Flexibility
December 5, 2013. NXP Semiconductors N.V. today introduced two new microcontrollers that allow developers to address late design changes to their system. The LPC11E37H and the LPC11U37H include an I/O Handler peripheral that offers designers the flexibility to add incremental peripheral functionality at any point during the design cycle. The I/O Handler peripheral can be easily configured to add I2S, I2C, UART, DMA, and other functionality to the MCU with little impact on CPU performance. Each microcontroller features a low-power 50-MHz ARM® Cortex-M0 processor with up to 128 KB of flash, 12 KB of SRAM, and 4 KB of EEPROM, with an additional Full-Speed USB device controller included on the LPC11U37H.
“With design cycles becoming shorter than ever, there are often unforeseen system changes that require additional MCU functionality late in the design,” said Ross Bannatyne, general manager, mass market microcontroller product line, NXP Semiconductors. “The new I/O Handler peripheral allows designers to easily add significant functionality, such as serial communications interfaces, at any time in the design cycle. The I/O Handler can even provide DMA (Direct Memory Access) or ADC threshold functionality to further optimize performance and power efficiency.”
The I/O Handler is configured using pre-compiled libraries that can be downloaded from NXP’s LPCware software and support website and are available for no additional charge.