Teradyne introduces the UltraFLEXplus to minimize time-to-market for complex digital devices
Teradyne on Sept. 4 introduced the UltraFLEXplus, the newest member of the UltraFLEX family of testers, and the first to include the PACE architecture.
NORTH READING, MA—Teradyne, a supplier of automated test solutions, on Sept. 4 introduced the UltraFLEXplus, the newest member of the UltraFLEX family of testers and the first to include the PACE architecture. The UltraFLEXplus addresses the emerging digital test requirements driven by the changes in artificial intelligence and 5G communications infrastructure.
Test characterization and production data volumes are overwhelming current tester architectures resulting in extended development cycles and longer production test times. To address this emerging challenge, Teradyne developed the PACE multi-controller architecture for the UltraFLEXplus. The PACE architecture includes revolutionary, patented technology that enables test engineers to debug and characterize complex devices far more efficiently, delivering new products to market faster with less engineering effort and better tester utilization.
The UltraFLEXplus combines the breakthrough PACE architecture with the industry’s leading IG-XL software, to ensure semiconductor companies are prepared to successfully handle these new test challenges. Teradyne's IG-XL software not only gives customers a comprehensive development environment, but also leverages the installed base of over 4,000 UltraFLEX testers. This allows the 10,000 active IG-XL-trained test engineers to develop flexible test programs.
“SOC devices are forecast to require up to eight times the test data in 2025 compared to 2018. This is true of both the amount of data needed to thoroughly test the device as well as the number of test results that have to be retained for post-test yield and performance analysis,” said Greg Smith, president of Teradyne’s semiconductor test division. “To get these devices to market and deliver industry leading test economics, we recognized a fundamental improvement in ATE architecture was needed.”