ASSET teams with Mentor on IJTAG, will offer workshops
ASSET InterTech chose the International Test Conference to highlight seamless interoperability between ASSET InterTech and Mentor Graphics’ Tessent products for the IEEE P1687 Internal JTAG (IJTAG) embedded instrumentation standard. The standard will allow engineers to debug and isolate issues in either a complex SoC or on the circuit board where the chip has been deployed.
Tim Caffee, ASSET’s vice president of design validation and test, said the IJTAG standard defines access to portable and re-usable embedded instruments. The standard, he said, has three components: a flexible serial instrument access architecture (called the network), a network description language (called Instrument Connectivity Language, or ICL), and an instrument vector language (called the Procedure Description Language, or PDL). The architecture comprises a controller, access network, and embedded instruments.
IJTAG applications today, Caffee said, include silicon validation and debug at the board level, at-speed flash programming of NOR and NAND devices via SPI or I2C, SerDes validation (including PCIe, SATA, PEG, and USB), and memory validation (including DDR3 and DDR4).
Caffee described an IJTAG flow and two-way validation process that ends finger-pointing as to whether a problem lies at the chip or board level. EDA companies such as Cadence, Mentor, and Synopsis handle IJTAG insertion, simulation, ATPG, and emulation in FPGAs; ASSET handles board validation, test, and debug; and all parties contribute to the middle ground of silicon test on ATE and silicon validation.
ASSET at ITC specifically demonstrated the use of IJTAG resources, including embedded instruments and a network connecting them, inserted into a chip with Mentor’s Tessent IJTAG solution. These instruments allow engineers to verify and characterize the functionality and performance of the SoC at the chip level. When deployed on a circuit board, ASSET’s ScanWorks tool provides a debug loop by accessing IJTAG resources to isolate problems in both the SoC and the circuit board. Issues found at the chip level can be corrected before additional devices are fabricated.
“This two-way debug feedback between chip and board eliminates any doubt about whether the faulty behavior is in the chip or on the board,” said Al Crouch, vice chairman of the IEEE P1687 IJTAG working group and a chief technologist for ASSET, in a press release. “Of course, conformance to the IEEE P1687 standard is critical to the interoperability between our ScanWorks tool and Mentor’s Tessent IJTAG solution. In my opinion, IJTAG will take a major step toward approval soon and once that happens, momentum will quickly increase for full industry adoption.”
“The complexity of today’s SoCs and the growing number of IP blocks integrated into these designs are making IJTAG a necessity if the industry is going to maintain its rapid pace of new product introductions, said Stephen Pateras, product marketing director at Mentor Graphics, in the press release. “Aligning Tessent IJTAG with ASSET’s ScanWorks is a big step toward enabling our customers to fully capitalize on the potential of the IJTAG standard.”
Caffee at ITC said ASSET and Mentor are committed to collaborating on several educational programs that will jump-start the adoption of IJTAG, including a series of workshops in major technology hubs in the U.S., Asia, and Europe. And ASSET is publishing several IJTAG eBooks authored by Al Crouch. A series of IJTAG workshops is currently being planned by ASSET and Mentor for the spring of 2015. Attendance at one half-day session is priced at $295. Following the morning workshop, a limited number of private consultations will be available with the experts who will be teaching the workshop.