ITC to span design verification through field test and process improvement

The International Test Conference convenes the week of October 20 in Seattle. As explained by general chair Michael Purtell and program chair Subhasish Mitra, “ITC addresses outstanding design, validation, and test challenges—ranging from immediate concerns blocking progress today to major obstacles in future technologies.”

ITC, they said, covers the complete product cycle:

  • design verification,
  • design-for-test,
  • design-for-manufacturing,
  • post-silicon validation and debug,
  • manufacturing test,
  • diagnosis,
  • failure analysis and yield improvement,
  • system testing at the hardware-software interface,
  • error detection and testing in the field,
  • hardware security and trust, and
  • process and system design improvements.

Events get started Sunday October 19 with six tutorials covering test of TSV-based stacked ICs (basic and advanced), mixed-signal DFT and BIST, high-speed I/O test, hardware security and test, and delay test. Monday will follow with tutorials on hierarchical test for SoCs; hierarchical scan compression; statistical and adaptive test; memory test and repair; test, diagnosis, and root-cause identification of failures for boards and systems; and RF testing. Also on Monday is a panel titled “Analog Design for Test: What is the real story?”

ITC proper gets started Tuesday with a keynote by Aart de Geus, chairman and co-CEO of Synopsys, titled “Testing Positive…for Complexity!” He will cover the advances in design, test, diagnosis, and yield optimization that are necessary to keep up with Moore’s Law.

The technical program will have 87 presentations (including invited talks), three panel sessions (including a plenary panel), an elevator session, two discussion sessions, a poster session, and two workshops covering 3-D IC test and defect and adaptive test analysis. Technical sessions will address new defect types, analog modeling and measuring, robust energy systems (including microgrids and grid resilience), adaptive test, security, test compression, RF test, embedded systems, big data, timing and power during test, MEMS test, high-volume manufacturing, jitter and nonlinearity, packaging and probing, memory repair, SoC test, printed-circuit-board test, ATPG, and functional test.

A Wednesday panel titled “Widsom from Giants” will draw on panelists’ combined 200 years of experience to describe how test is driving the success of the semiconductor industry. The Thursday plenary keynote by Patrice Godefroid, principal researcher at Microsoft Research, will cover automated software testing for the 21st century. He will discuss the challenge presented by automatic code-driven test generation and comment on practical tools that have become available—addressing topics like symbolic execution, dynamic analysis and runtime instrumentation, model checking and systemic state-space exploration, and automated constraint solving using SMT solvers.

Exhibitors will highlight everything from EDA software to test hardware and complete test solutions. The exhibit floor will also host a corporate forum that will give companies an opportunity to present their new developments in test equipment, services, tools, and methodologies. In addition, the Exhibit Hall Passport Program, returning from last year, will give attendees an opportunity to win prizes by visiting exhibitors’ booths.

AITC reports that 55 organizations have signed up to exhibit, with more expected. New exhibitors to date include Innovative Circuits Engineering., Ateeda, Presto Engineering, Leeno Industrial, ProbeLogic, NHK, and W5 Engineering.

Several exhibitors have already announced plans for the show:

  • Mentor Graphics announced that a key focus of the company at the show will be “The Next Big Thing in Test Compression,” and Nilanjan Mukherjee, engineering director for the Test Synthesis Group in the Silicon Test Solutions division of the company, will elaborate on the topic at a Monday evening reception.
  • Optimal+ will describe how its Big Data analytic solutions are being used by industry leaders to measurably improve their product yield, quality, and productivity. And AMD will describe in the Corporate Forum how it has used Optimal+ in its manufacturing operations.
  • Xcerra will highlight its LTX-Credence testers, Multitest test handlers and test interface products, Everett Charles Technologies probes, and Xcerra fully integrated test cell solutions.
  • Addressing the emerging Internet of Things, Syntricity will highlight its dataConductor, a scalable solution architected to handle massive data growth from trillions of devices.
  • Synopsys will highlight its synthesis-based test solution; a Monday evening SIG event will be a forum for presentations from Saman Adham, TSMC; Naveen Mysore, Avago Technologies; Nelly Feldman, STMicroelectronics; and Ying Yen Chen, Realtek Semiconductor.
  • Qualtera will demonstrate the latest release of Silicondash, an efficient tool for accelerating product yield ramps and securing quality in high-volume manufacturing and test operations.

Cadence will not be exhibiting, but as an ITC Silver Sponsor, will have experts on hand to showcase its differentiated DFT solutions within the Cadence Encounter RTL Compiler cockpit, Cadence Encounter True-Time ATPG, and Cadence Encounter Diagnostics.

Test Week activities conclude with workshops Thursday evening and Friday on testing 3-D stacked ICs and adaptive test and data analysis.

Visit http://www.itctestweek.org/ for more information and to register.

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