DesignCon participants target signal, power integrity

(Updated January 29) DesignCon takes place January 28-31 in Santa Clara with participants targeting signal-integrity issues accompanying high-speed chip, package, board, cable, and system design. More than 150 exhibitors will showcase a variety of cutting-edge high-speed design solutions including ones for modeling and simulation and test and measurement. To prepare for the event, read EE-Evaluation Engineering's January print and online-exclusive reports of high-speed serial-I/O test.

As of January 25, companies including Agilent Technologies, Anritsu, ANSYS, PacketMicro, Tektronix, and Teledyne LeCroy have announced some specifics about the products and technologies they are planning to highlight at the event.

Agilent, for example, has announced it will exhibit its range of high-speed digital products that help engineers design, simulate, analyze, debug, and achieve compliant gigabit digital designs. The company will show its new Agilent EEsof EDA’s Controlled Impedance Line Designer, J-BERT M8020A, and TDR/TDT solutions to the public for the first time. (Update, January 27: Agilent today released details on its new N1055A 35/50-GHz time-domain reflectometry and transmission module for the Agilent 86100D DCA-X platform. Visit here for more.)

Agilent will also display and demonstrate high-speed/high-performance oscilloscopes, logic analyzers, protocol analyzers, a boundary-scan analyzer, EDA software, and RF and microwave network analyzers. Agilent will also present 10 separate 40-minute training sessions.

“Agilent recognizes the unique value DesignCon brings to the many customers from the high-speed digital world,” said Agilent’s Doru Popescu, market segment manager. “We will showcase our latest products that provide design and test engineers with the best solutions to challenging digital problems. We’ll continue to do that as we prepare to become Keysight Technologies and separate from Agilent later this year.”

Tektronix said it will be demonstrating support for mobile, server, and datacom platform testing, addressing such topics as PCI Express 3 compliance, DDR4 validation, 100G datacom test, and Wi-Fi 802.11ac test. Specifically, the company will highlight its recent acquisition of Picosecond Pulse Labs and will also likely demonstrate recently expanded capabilities for M-PHY receiver test. (See related article “UFS PHY and Protocol Testing for Compliance” by Chris Loberg, a senior technical marketing manager at Tektronix.)

Tektronix representatives will also be participating in panels titled “Battle on the Chip: Embed vs. De-Embed” and “Optical System Technologies and Integration” and will present papers on topics such as 100G margins, stressed receiver testing, and correlation of simulation and measurement results.

(Update, January 28: Tektronix today announced a fully automated compliance test and debug solution for the recently released HDMI 2.0 specification. Visit here for more.)

Anritsu at its booth will have demonstrations of BER, emphasis, and jitter measurements conducted on an Avago Technologies 25-Gb/s evaluation board with electrical SerDes, parallel optical links, and various channel trace lengths using the MP1800A BERT. A VectorStar station, including the Wild River Technology CMP, will highlight the importance of simulation-measurement correspondence.

And the PacketMicro booth will feature demonstrations of Anritsu’s high-performance VectorStar with PacketMicro’s innovative ruggedized RF probes for bench-top testing of large PCBs. PacketMicro’s HSProbe family is designed for direct probing on top of circuit components or test pads on an uneven surface.

VectorStar will also be part of a workshop titled “Practical Measurements of Dielectric and Loss of PCB Materials at High Frequencies,” which intended to help designers better understand the low-loss materials properties in high-frequency applications for more efficient designs.

Anritsu personnel will also participate on several technical sessions, including ones on bit-error-rate test, simulation-measurement correspondence, active optical cable test, and test of systems employing 4PAM, 8PAM, and quadrature amplitude modulation (QAM).

(Update, January 29: Anritsu announced its VectorStar vector network analyzer served in a DesignCon workshop conducted by technologists from DuPont and Rogers. Click here for more.)

Teledyne LeCroy said it will be presenting a 100-GHz oscilloscope preview and technology discussion. Product exhibits will emphasize the speed, performance, and analysis capabilities of the company's oscilloscopes and signal-integrity test solutions. Products featured include 10 Zi oscilloscopes, with 65-GHz bandwidth on up to 40 channels, and 12-bit high-definition HDO oscilloscopes. Applications highlighted include multilane serial-data analysis; end-to-end compliance test for PCI Express, and DDR4 signal-integrity and timing analysis.

Teledyne LeCroy said it will also be contributing significantly to the technical conference with nine peer-reviewed technical presentations. Attendees can meet the presenters for follow-up and discussion at the company's booth, where a series of 15-minute talks will be held over the two days of the exposition.

(Update, January 28: Teledyne LeCroy at DesignCon today introduced the Voyager M310, a comprehensive protocol analyzer exerciser platform for testing next generation SuperSpeed USB systems. Click here for more.)

In addition, ANSYS and its subsidiary Apache Design will exhibit modeling, co-analysis, and advanced optimization simulation solutions for chip-package-system convergence. Demonstrations will focus on advanced methodologies and techniques for high-speed signal-analysis and optimization, system-wide power-delivery network integrity, and thermal analysis for 3-D/stacked-die designs.

ANSYS technologists will also be involved in the technical conference, addressing topics such as thermal co-analysis of 3-D ICs, periodically loaded transmission lines, and a reverse Nyquist approach to understanding low-frequency information in scattering matrices.

(Update, January 29: ANSYS at DesignCon today debuted new functionality for ANSYS SIwave. Click here for more.)

100 Sessions in 14 Tracks

Show sponsor UBM Tech said it is welcoming thousands of influential members of the chip, package and board design communities to DesignCon, whose technical conference this year will feature more than 100 conference sessions organized under one of 14 tracks designed to address the latest developments in a range of industry-specific categories including signal and power integrity, PCB design tools and methodologies, parallel and memory interface design, high-speed serial design, wireless and photonic design and integration, and jitter and crosstalk.  To help attendees manage their time and priorities, DesignCon is providing an interactive schedule builder that is compatible with the DesignCon Mobile App.  Available in iPhone/iPad, Android, and mobile web versions, the DesignCon Mobile App automatically populates with individuals’ online Schedule Builder selections, as well as provides users with an attendee directory, exhibitor listings, location-based check-ins, badging, and Twitter and Facebook interactivity.

In addition to exhibits and technical presentations, DesignCon will host keynote speakers from Intel, Micron Technologies, and XPRIZE. DesignCon is also reinforcing its commitment to STEM with two new initiatives: a Next-Gen volunteer program geared toward students and emerging engineers and a Bay Area Girl Geek Dinner on Thursday, January 30.

http://www.designcon.com/santaclara/

(Update, January 29: See related post “Intel VP praises DesignCon attendees.”)

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