Open-Silicon Improves Test Quality with Tessent Cell-Aware Test
September 11, 2013. Mentor Graphics Corp. announced at the International Test Conference that ASIC design company Open-Silicon has used the Tessent TestKompress product with Cell-Aware Test to improve test quality of SoC designs. By using the Tessent TestKompress product, Open-Silicon succeeded in detecting and resolving defects previously undetected using traditional techniques. Open-Silicon has also deployed the Tessent MemoryBIST product for at-speed testing, diagnosis, and repair of embedded memories.
“As our customers move to smaller process nodes and larger SoC designs, the challenge of detecting subtle defects becomes more complex,” said Taher Madraswala, senior vice president of engineering for Open-Silicon. “To meet the demand for very low DPM, we need tests that not only detect defects at the standard-cell boundaries, but also capture defects within the cell. The Tessent Cell-Aware Test solution gives us this capability without increasing our test cost significantly.”
Cell-Aware Test is a transistor-level test methodology that overcomes the limits of traditional stuck-at and transition fault models and associated test patterns by targeting specific shorts, opens, and transistor defects internal to each standard cell, resulting in significant reductions in defect (DPM) levels.
Open-Silicon provides its customers with fully tested parts, and the Mentor Cell-Aware Test capability and the Tessent MemoryBIST solution enhance their ability to provide more reliable silicon to their customers. Open-Silicon has used the Tessent TestKompress Cell-Aware Test capability to detect cell-internal defects that were not detected using traditional silicon test methods, which successfully reduced their defective parts-per-million (DPM).
“Cell-Aware Test is proving its value to companies like Open-Silicon who need to reduce DPM levels” said Steve Pateras, product marketing director at Mentor Graphics. “We are continuously enhancing our Tessent DFT solutions to achieve the highest test quality while reducing test development effort and production test cost.”