GOEPEL Integrates JTAG and Mixed-Signal Test in One Chip

May 24, 2013. GOEPEL electronic has introduced CION LX, a new generation of JTAG transceiver IC. The chip provides ultralow voltage characteristics, offering a tester-per-pin architecture based on diverse Boundary Scan standards such as IEEE 1149.1, IEEE 1149.6, and IEEE 1149.8.1, in combination with additional digital and analog test instruments. Various operation modes enable a wide range of applications of the IC as bus transceiver, pin driver, and system monitor. For flexible signal adaptation, different interface types with programmable transceiver parameters have been integrated into the chip.

“The third generation of JTAG transceivers is our approach to solve the problem of ultralow voltage applications. Additionally, with the CION LX we have succeeded in combining various analog and digital test instruments with one extensive boundary scan architecture in a unique way,” said Thomas Wenzel, managing director of GOEPEL electronic’s boundary scan division. “At the same time, our new IC provides an excellent starting position for the development of more powerful I/O modules.”

The CION LX was developed in 0.35-µm mixed-signal CMOS technology and provides four independent I/O ports. Each port can be individually operated in a voltage range from 0.9 V to 3.6 V. The integrated boundary scan architecture supports IEEE 1149.1, IEEE 1149.6 and IEEE 1149.8.1, at a maximum TCK frequency of 100 MHz. In addition to the single-ended pins, the CION LX provides differential signals as well as interfaces with increased driver ability. Four operation modes enable the IC‘s flexible utilization as purely serially controlled JTAG transceiver, parallel I/O buffer, latched bus transceiver, and pin driver.

Furthermore, instruments such as digitizer, arbitrary waveform generator, event counter, frequency meter, and toggle detectors are integrated into the CION LX. These instruments can be accessed, depending on operation mode, either serially via the JTAG Test Access Port (TAP) or a parallel control bus. The instruments can be activated simultaneously to boundary scan operations and per test channel. For each channel, pull-up and pull-down resistors can be additionally connected. Moreover, there’s the opportunity to program the drivers‘ slew rates.

The CION LX is currently available as a sample. First series deliveries are planned for Q3 2013. A QFN housing with 116 pins will be used. Additionally, there will be a version with 64 pins compatible to the predecessor model footprint.

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