March 14, 2013. GOEPEL electronic announced its IP-based ChipVORX technology has been extended to execute bit-error-rate test (BERT). The automated solution enables FPGA embedded instruments in the form of soft cores to support the test and design validation of high-speed I/O. Users can now evaluate the transmission channel quality via measurement of the bit error rate. A graphical evaluation via eye diagram facilitates design validation.
ChipVORX takes over the complete process flow, starting with the target FPGA programming, IP to pin configuration, and instrument control as well as data processing and the final IP unloading. In the debug mode, the BERT parameters can be changed interactively for immediate effect without design synthesis.
“Our announcement on ChipVORX prototype demonstration for bit error rate tests in November last year generated an enormous interest, which finally reflects this technique‘s strategic importance for quality assurance of modern high-speed designs,“ said Thomas Wenzel, GOEPEL’s managing director of the JTAG/boundary scan division.
Chip embedded Instruments are permanently integrated or temporarily implemented test and measurement functions in an integrated circuit. Virtually, they are the counterpart to external instruments as they don’t require invasive contacting by means of probes or nails. Hence, the problem of signal distortion in high-speed designs by parasitic contacting effects is omitted. Chip embedded instruments are part of GOEPEL's so called Embedded System Access (ESA) technologies, which support validation, test, and debug as well as programming of complex boards and systems. They can be utilized throughout the entire product life cycle, enabling improved test coverage at reduced costs.
ChipVORX is an IP-based technology for implementation, access, and control of chip embedded instruments via IEEE 1149.x/JTAG. It also supports FPGA embedded instruments in the form of soft cores. The ChipVORX library currently contains more than 300 different test and measurement instruments for all leading FPGA platforms. Some of these instruments are frequency meters and high-speed flash programmers as well as IP for at-speed access test of dynamic RAM devices.
The BERT instruments development as prototypes and their integration into respective system software is the result of a strategic cooperation between GOEPEL electronic and Testonica Lab. The ChipVORX IP models for BERT will be supported in SYSTEM CASCON starting from version 4.6.3 and are activated via the license manager. SYSTEM CASCON is GOEPEL electronic’s professional JTAG/boundary-scan development environment with currently more than 45 fully integrated ISP, test, and debug tools. In terms of hardware, ChipVORX is supported in the SCANFLEX platform.