Cabled PCI Express For Measurement Applications

The PCI Special Interest Group (PCI-SIG), developer of the PCI and PCI Express (PCIe) specifications, recently announced the PCIe External Cabling 1.0 Specification, which extends PCIe architecture outside the box. Cabled PCIe is a cabled serial bus used for high-performance interconnect of system components.

Because cabled PCIe is based on PCIe, it provides a scalable, high-bandwidth, low-latency bus. The possibility of extending PCIe over a cable creates opportunities in high-performance measurement and automation applications that use a host PC for processing and analysis.

For example, cabled PCIe connects a host PC to a PXI chassis with sustained transfer rates of more than 800 MB/s. The high performance, low cost, and easy connectivity of cabled PCIe make it ideal for many applications that were limited by the lack of high-speed interconnect.

Cabled PCIe establishes a standard method of using PCIe technology over a cable by defining cable connectors, copper cabling attributes and electrical characteristics, connector retention, identification, and labeling. It conforms to the PCIe 1.1 base and electromechanical specifications, enabling high data rates between PCIe subsystems.

Standard cables and connectors have been defined for x1, x4, x8, and x16 links. The cable provides sideband signaling to maintain compatibility with existing silicon and software, allowing developers to leverage the existing PCIe base.

Extending PCIe from box to box and over longer distances is the goal of cabled PCIe. It provides a simple, yet high-performance bus for expanding PC and measurement I/O. PCI-SIG completed and released the cabled PCIe specification in February 2007.

PCIe
Developed and released by Intel more than a decade ago, the original PCI bus operated at 33 MHz and 32 bits with a peak theoretical bandwidth of 132 MB/s. It used a shared bus topology bus bandwidth is shared among multiple devices to enable communications among the different devices on the bus. As technology evolved, new bandwidth-hungry devices began starving other devices on the same shared bus. Gigabit LAN cards, for example, can monopolize up to 95% of available PCI bus bandwidth.

To provide the bandwidth required by these modern devices, an industry consortium of PC and peripheral vendors developed PCIe and began shipping it in standard desktop PCs in 2004. Today, most PCs from leading suppliers have multiple PCIe slots with varying lane widths. The most notable PCIe advancement over PCI is its point-to-point bus topology.

Unlike PCI, which divides bandwidth among all devices on the bus, PCIe provides each device with its own dedicated data pipeline. Data is sent serially in packets through pairs of transmit-and-receive channels called lanes, which enable 250-MB/s bandwidth per direction per lane. Multiple lanes can be grouped together into x1, x2, x4, x8, x12, x16, and x32 lane widths to increase bandwidth to the slot.

The initial signaling frequency in the specification, 2.5 Gb/s, provides, with a x16 slot, 30 times the usable bandwidth of 32-bit, 33-MHz PCI. With advances in silicon technology, this signaling frequency is expected to increase to 10 Gb/s, the practical limit for signals in copper (Figure 1).

Aero Fig1 Worked

Figure 1. Bandwidth vs. Latency for Various Buses

In addition to dedicated and scalable bandwidth, PCIe also is the industry's highest performing bus. The two factors that generally characterize the performance of the bus are latency and bandwidth. Latency is a measure of how long it takes for a device to reply to a request. Bandwidth is a measure of how much data can be transferred across the bus in a given amount of time.

PCIe has the industry's best bandwidth and latency specifications compared to other standard buses. It is the combination of latency and bandwidth that affects the speed of the measurement system.

Software Compatibility
PCIe maintains software compatibility with traditional PCI. The configuration space and programmability of PCIe devices are unchanged from the traditional PCI methodology. In fact, all operating systems are able to boot without modification on a PCIe architecture.

Because the PCIe physical layer is transparent to application software, programs originally written for PCI devices can run unchanged on PCIe devices that have the same functionality, and engineers can use PCI and PCIe devices together in the same system.

This backward compatibility of PCIe software with PCI is critical in preserving the software investments of both vendors and users.

Cabled PCIe
Cabled PCIe has the most potential to be the next-generation peripheral bus for servers, desktops, and laptops. It offers the following advantages:
• High bandwidth of 4 GB/s.
• Low latency of 300 ns to 700 ns.
• Application software and operating systems that run without changes.
• Only standard designed for chip-to-chip, board-to-board, and box-to-box applications.
• Wide use in standard PCs providing low implementation costs.

The cabled PCIe specification offers guidelines for a practical cable length but currently does not set a maximum cable distance.

Measurement and Automation
Cabled PCIe provides higher performance and a more compactly designed external bus for connecting distributed measurement and automation systems. PXI is an industry standard for modular instrumentation and robust control systems that uses cabled PCIe in the form of Multisystem eXtension Interface (MXI) to connect multiple Eurocard chassis, desktop PCs, or laptops.

MXI-Express uses cabled PCIe to connect a PXI chassis to a host PC or laptop for external control. MXI-Express remote controllers are available now in x1 and x4 configurations, which provide more than 800 MB/s of sustained throughput.

Future Implementations
Engineers can use cabled PCIe as a high-performance, low-cost interconnect in several instrumentation applications. For example, cabled PCIe accommodates high-speed data transfer when interconnecting two traditional stand-alone instruments, connecting a traditional stand-alone instrument to a PC, or connecting a PC to PXI chassis. Depending on whether the instruments connected to either end of a cabled PCIe interconnect have local CPUs, cabled PCIe can be classified into two different modes:

Aero SideHost Mode
The host mode addresses instruments that are endpoints only. The clock, addresses, and device enumeration are extended to the instrument by the host using a transparent bridge. Using MXI-Express to connect a PC to a PXI chassis is an example of this implementation. The PC CPU allocates the necessary addresses and resources to all devices in the PXI chassis.

Local Mode
The local mode addresses instruments with embedded CPUs via the PCIe nontransparent bridge (NTB). Connecting a PC to a traditional stand-alone instrument with an embedded CPU is an example of a local mode application.

With two CPUs involved in the setup, there are conflicts with clocking, addressing, and device enumeration. Using a PCIe NTB ensures that the clocking, addressing, and device enumeration are aligned between the two instruments.

Synthetic Instrumentation
Because cabled PCIe is designed for box-to-box applications, engineers can use it to connect a PC to traditional instruments. As the trend for more software-centric instrumentation increases, the need for a high-speed connection to a host processor is even greater.

The U.S. Department of Defense (DoD), for example, has coined the term synthetic instrumentation (SI) to describe these software-centric systems and created a committee called the Synthetic Instrument Working Group (SIWG) to define standards for synthetic instrument system interoperability. SIWG defines SI as  a reconfigurable system that links a series of elemental hardware and software components with standardized interfaces to generate signals or make measurements using numeric processing techniques.• 
(Figure 2)

Aero Fig2 Worked

Figure 2. Synthetic Instrument RF Block Diagram

SIWG primarily focuses on the SI concepts as applied to RF stimulus and measurement systems. Data-intensive applications such as RF testing require a high-bandwidth, low-latency bus to connect the IF digitizers to the processor.

For example, digitizing a 50-MHz RF signal typically needs 200 MB/s of bandwidth (14-bit A/D, 2 bytes/per sample). For an input and output channel, this grows to 400 MB/s. And for increasingly common multichannel, or multiple input, multiple output (MIMO), applications, the bandwidth required can quickly scale to gigabytes per second. Engineers have selected PCIe and cabled PCIe in particular for this high-speed link because of excellent technical capabilities, wide commercial adoption, and low-cost infrastructure.

SIWG considered several high-speed serial interconnect technologies for data movement in ATE systems before selecting cabled PCIe. The committee evaluated several criteria including latency, bandwidth, supported communications schemes, quality of service, cable distance, cost, applications supported, and longevity.

Conclusion
Cabled PCIe provides a scalable, high-bandwidth, low-latency bus for chip-to-chip, board-to-board, and box-to-box applications. In addition, it opens up a new, larger, and faster pipe to the host PC, at a very low cost so more applications can take advantage of user-defined software and hardware for measurement processing, analysis, and control.

Today engineers can use cabled PCIe to connect host PCs to PXI chassis with MXI-Express. It currently sustains transfer rates of 208 MB/s for a x1 link and rates greater than 800 MB/s for a x4 link with a maximum cable length of 7 m. High-bandwidth, low-latency measurement and automation applications should experience significant performance improvements when using cabled PCIe.

About the Author
Murali Ravindran is a PXI product manager at National Instruments. He started his career at NI in 2004 in the Engineering Leadership Program as an applications engineer and holds a master's in electrical engineering and an M.B.A. in entrepreneurship from the University of Oklahoma. Before joining NI, Mr. Ravindran worked for three years as a research assistant in the Center for the Study of Wireless Electromagnetic Compatibility and as a business intern in a start-up biotech company. National Instruments, 11500 N. Mopac Expwy., Austin, TX 78759, 512-683-5085, e-mail: Murali.Ravindran@ni.com

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