San Francisco, CA. Imec’s annual Technology Forum kicked off today in connection with SEMICON West with two announcements focused on how 2D materials can be used to scale FETs for very advanced technology nodes and an electrically functional solution for the 5-nm back-end-of-line (BEOL).

First, imec has demonstrated an electrically functional 5-nm BEOL solution—a full dual-damascene module in combination with multi-patterning and multi-blocking. Thanks to innovations in materials, process schemes, new BEOL architectures, and system/technology co-optimization, imec reports having overcome the RC delay challenges.

Second, imec and its partners have uncovered a path to unlock 2D materials-based FETs for high performance logic. With partners at KU Leuven and Pisa University, imec has performed what it calls the first material-device-circuit level co-optimization of FETs based on 2D materials for high-performance logic applications scaled beyond the 10-nm node.

With regard to the electrically functional solution for the 5-nm BEOL, imec said that as R&D progresses towards the 5-nm technology node, the tiny Cu wiring schemes in the chips’ BEOL are becoming more complex and compact. Shrinking the dimensions also reduces the wires’ cross-sectional area, driving up the resistance-capacitance product (RC) of the interconnect systems and thus increasing signal delay. To overcome the RC delay challenge and enable further improvements in interconnect performance, imec is exploring new materials, process modules, and design solutions for future chip generations.

One viable option is to extend the Cu-based dual-damascene technology—the current workhorse process flow for interconnects—into the next technology nodes. imec has demonstrated that the 5-nm BEOL can be realized with a full dual-damascene module using multi-patterning solutions. With this flow, trenches are created with critical dimensions of 12 nm at 16 nm.  Metal-cuts (or blocks) perpendicular to the trenches are added in order to create electrically functional lines, and then the trenches are filled with metal. Area scaling is further pushed through the introduction of fully self-aligned vias. Moreover, aggressive design rules are explored to better control the variability of the metal tip-to-tips (T2Ts).

Beyond 5 nm, imec is exploring alternative metals that can potentially replace Cu as a conductor. Among the candidates identified, low-resistive ruthenium (Ru) demonstrated great promise. The imec team has realized Ru nanowires in scaled dimensions, with 58-nm2 cross-sectional area, exhibiting a low resistivity, robust wafer-level reliability, and oxidation resistance—eliminating the need for a diffusion barrier.

“The emergence of RC delay issues started several technology nodes ago, and has become increasingly more challenging at each node. Through innovations in materials and process schemes, new BEOL architectures, and system/technology co-optimization, we can overcome this challenge as far as the 5 nm node,” said Zsolt Tokei, imec’s director of the nano-interconnect program. “Imec and its partners have shown attainable options for high density area scaled logic blocks for future nodes, which will drive the supplier community for future needs.”

For the longer term, imec is investigating different options including but not limited to alternative metals, insertion of self-assembled monolayers, or alternative signaling techniques such as low-energy spin-wave propagation in magnetic waveguides, exploiting the electron’s spin to transport the signal. For example, the researchers have experimentally shown that spin waves can travel over several micrometers, the distance required by short and medium interconnects in equivalent spintronic circuits.

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, and TSMC.

The path to unlock 2D materials-based FETs

With regard to imec’s collaboration with scientists from KU Leuven in Belgium and Pisa University in Italy, imec reports it and its partners have performed the first material-device-circuit level co-optimization of FETs based on 2D materials for high-performance logic applications scaled beyond the 10-nm technology node. imec also presented novel designs that would allow using mono-layer 2D materials to enable Moore’s law even below 5-nm gate length.

2D materials, a family of materials that form two-dimensional crystals, may be used to create the ultimate transistor with a channel thickness down to the level of single atoms and gate length of few nanometers. A key driver that allowed the industry to follow Moore’s Law and continue producing ever more powerful chips was the continued scaling of the gate length. To counter the resulting negative short-channel effects, chip manufacturers have already moved from planar transistors to FinFETs. They are now introducing other transistor architectures such as nanowire FETs. The work reported by imec looks further, replacing the transistor channel material with 2D materials as some of the prime candidates.

To fit FETs based on 2D materials into the scaling roadmap, it is essential to understand how their characteristics relate to their behavior in digital circuits. In the paper published in Scientific Reports,* the imec scientists and their colleagues presented guidelines on how to choose materials, design the devices, and optimize performance to arrive at circuits that meet the requirements for sub-10-nm high-performance logic chips. Their findings demonstrate the need to use 2D materials with anisotropicity and a smaller effective mass in the transport direction. Using one such material, monolayer black-phosphorus, the researchers presented novel device designs that pave the way to even further extend Moore’s law into the sub-5-nm gate length. These designs reveal that for sub-5-nm gate lengths, 2D electrostatics arising from gate stack design become more of a challenge than direct source-to-drain tunneling. These results are very encouraging, because in the case of 3D semiconductors, such as Si, scaling gate length so aggressively is practically impossible.

“2D materials, with the atomically precise dimension control they enable, promise to become key materials for future innovations. With advancing R&D, we see opportunities emerging in domains such as photonics, optoelectronics, (bio) sensing, energy storage, photovoltaics, and also transistor scaling. Many of these concepts have already been demonstrated in the labs,” said Iuliana Radu, distinguished member of technical staff at imec. “Our latest results presented in Scientific Reports show how 2D materials could be used to scale FETs for very advanced technology nodes.”

*T. Agarwal, G. Fiori, B. Soree, I. Radu, P. Raghavan, G. Iannaccone, W. Dehaene, and M. Heyns, “Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes” Scientific Reports (SREP-16-50433).

This work was supported by imec’s industrial affiliation programs on core CMOS including key partners GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, and TSMC and by the European GRAPHENE FLAGSHIP core 1 (Contract No. 696656).

See related article, “ITFUSA kicks off SEMICON West putting a human face on technology.”

imec targets 5-nm BEOL and 2D-materials-based FETs
Rick Nelson
Rick became Executive Editor for EE in 2011. Previously he served on several publications, including EDN and Vision Systems Design, and has received awards for signed editorials from the American Society of Business Publication Editors. He began as a design engineer at General Electric and Litton Industries and earned a BSEE degree from Penn State.