On-Chip Instrumentation Augments ATE
A variety of hardware and software products has been introduced this year that significantly enhances semiconductor test capability. Products highlighted at SEMICON West in July and the International Test Conference (ITC) in September indicate the breadth of choices test engineers have when developing semiconductor test strategies. Those products include ATE systems, design-automation tools, yield monitoring software, and tools that build on the IEEE 1149.1 boundary-scan standard and its extensions.
Teradyne announced the J750Ex-HD production test system (Figure 1) at SEMICON West. The J750Ex-HD includes system enhancements and new High Density (HD) instruments, which can be used with installed J750 and IP750 test systems to seamlessly run new and existing test programs. Teradyne said it has received multiple orders from multiple customers and began shipments of the new HD instruments and J750Ex-HD systems in the second quarter of 2013.
Figure 1. J750Ex Semiconductor Test System
Greg Smith, general manager of Teradyne’s complex SoC business unit, described the new tester as the next generation of the J750, originally introduced in 1998. “It’s a whole platform refresh,” he said. Compared with the previous generation introduced in 2007, it doubles the digital density, accommodates five times as many power supplies, and adds new RF and data-converter capabilities. The platform, he said, finds use in microcontroller test and in wafer sort for SoCs and mobile communications devices, for which customers will perform final test using a tester like Teradyne’s UltraFLEX or Advantest’s V93000.
Jason Zee, general manager of Teradyne’s consumer business unit, cited some factors driving the need for the refresh. Multisite test drives the need for higher digital densities, and, he said, microcontrollers, in support of the Internet of Things, are incorporating RF circuitry to implement communications capabilities in accordance with standards such as ZigBee. And finally, the microcontrollers also increasingly incorporate more data converters and more accurate ones, such as 16-bit delta-sigma ADCs. MCUs could sport as many as 10 such converters within the next five years.
Smith described the J750 as probably the most successful platform ever offered, with 4,000 already in the field at the time of the new version’s launch. The refresh, he said, easily readies the platform for the next five or 10 years.
Specific features of the new J750Ex-HD include the HSD800 third-generation digital instrument, which provides 128 high-speed digital channels, scalable to 2,048 channels per system. The instrument also introduces DIB Access, a feature allowing unique tester resources, including high-voltage and digital source and signal capture pins, to be connected without external hardware. DIB Access reduces load-board complexity, shortening time-to-market and simplifying concurrent test to increase overall test-cell throughput. In addition, the 72-channel HD CTO is a precision DC and analog instrument with graphical programming templates and debug tools to simplify converter testing and other precision DC measurements. IG-XL 3.60 software extends pushbutton program scalability to 512 sites. The zero-footprint, air-cooled system minimizes floor-space requirements. The new system’s architecture maintains pin and program compatibility with existing J750Ex device programs.
Synopsys announced DFTMAX Ultra (Figure 2), part of Synopsys’ synthesis-based test solution, at ITC. According to Robert Ruiz, senior product marketing manager, DFTMAX Ultra reduces test costs by 20x or more by offering two to three times higher compression while supporting faster scan chains with fewer test pins. He cited several driving factors. Designs are more complex, with 5 million or more IP instances, with IP use growing 50% or more with each process node, and 30% of designs and cores have less than seven test pins. In addition, because of subtle defects (such as resistive bridges, metal voids, FinFET opens, and litho hotspots), more than 50% of failures cannot be found with standard tests. As for ATE, some testers can run scan patterns at 200 MHz or more, although half of the designs support 50 MHz or lower.
Figure 2. DFTMAX Ultra
DFTMAX Ultra, he said, addresses all these issues. Higher compression and hierarchical SoC test capabilities support higher design complexity, and DFT compression that operates as fast as scan takes advantage of higher tester performance. Higher compression also supports the additional patterns that advanced fault models use to reveal subtle defects. In addition, higher compression permits effective test despite fewer test pins—as few as one scan-in/out pair.
Several users shared their experiences on both DFTMAX Ultra and the newly announced DesignWare STAR Hierarchical System at the 21st annual Synopsys Test Special Interest Group meeting in Anaheim, CA, held Sept. 9 in conjunction with ITC.
Synopsys’ DFTMAX Ultra contains recently developed technology that efficiently streams compressed test data in and out of the design-for-test (DFT) circuitry, significantly lowering the amount of data required to achieve high manufacturing test quality of silicon parts. The tool-generated architecture requires fewer test pins and enables silicon parts to operate at higher frequencies while in test mode. As a result, engineers can test more die in parallel and reduce the time required to test each die. For superior quality of results and faster turnaround time, design teams use DFTMAX Ultra together with the Synopsys Galaxy Implementation Platform suite of tools, concurrently optimizing and performing intelligent trade-offs among speed, area, power, test, and yield.
At ITC, Synopsys also announced the availability of its DesignWare STAR Hierarchical System, an automated hierarchical test solution for efficiently testing SoCs, including ones with analog/mixed-signal IP, digital logic blocks, memory, and interface IP.
Sandeep Kaushik, senior product marketing manager at Synopsys, described the need for the STAR Hierarchical System. “Ad hoc test integration of IP and cores does not scale,” he said. “It lacks automation and relies on direct I/O access.” In contrast, the STAR Hierarchical System reduces test integration time by automatically creating a hierarchical network based on IEEE test standards (IEEE 1500, IEEE 1149.1, and IEEE P1687) that is managed by a modular server to access and control the test resources in the entire SoC. It improves test quality of results (QoR), including optimizing test time and power through flexible test scheduling.
Roberto Mattiuzzo, SoC test and diagnosis group manager at STMicroelectronics, reported that the STAR Hierarchical System, by automating IP test integration in the SoC and enabling the reuse of IP-level test patterns at the SoC level, cut weeks off design and the DFT cycles. He also said that the solution supports upcoming standards for accessing embedded SoC DFT structures, thereby accommodating board-level test.
The STAR Hierarchical System creates user-configurable IEEE 1500 interfaces in RTL for each IP and logic block in the SoC and integrates them with a top-level control module or server while maintaining a standard interface at every design hierarchy level. For designs with multiple levels of hierarchies, the solution offers a modular server in the desired hierarchy, instead of a single top-level server, to achieve test closure at the design hierarchy while minimizing the top-level signal routes. By utilizing existing, broadly adopted IEEE test standards, the STAR Hierarchical System enables easy integration of the SoC test resources, allowing global design teams concerned with different areas of the SoC to work more efficiently.
The automatic creation of a streamlined hierarchical network and unified standard test interfaces, controlled by a central or modular server, improves area and signal routing. In addition, the STAR Hierarchical System ports IP-level test patterns to the SoC level, leveraging the IEEE 1500 network for IP access, which eliminates the need to regenerate patterns and alleviates the capacity bottlenecks posed by large SoCs. Achieving test closure at the IP level and at all design hierarchy levels, as well as increased controllability and observability at the periphery of the IP and logic blocks, improves test QoR for large SoCs.
The STAR Hierarchical System leverages IP debug test modes and enables diagnostics control and access from the SoC level. Additionally, it helps improve SoC yield by enabling e-fuse programming through the server for calibration and trimming of analog/mixed-signal IP. The STAR Hierarchical System is compliant with the proposed IEEE standard P1687, which allows reuse of embedded test instruments for system-level debug.
Kaushik said future Synopsys DesignWare analog and mixed-signal IP, such as USB, DDR, and PCIe, will be delivered ready-to-use with the STAR Hierarchical System. This will enable designers to automatically create IEEE 1500 interfaces, integrate IP test structures on an SoC, and use hierarchical testing, he explained.
Mentor Graphics highlighted its Tessent TestKompress, Tessent MemoryBIST, and Tessent Hybrid TestKompress/LogicBIST products at ITC. Stephen Pateras, product marketing director at Mentor, said the company’s worldwide test and DFT market share has risen from 27% in 2000 to 54% in 2012 (an estimate based on data from Gary Smith at EDAC). He attributed the increase to Mentor’s introduction of embedded test compression in 2001 and diagnosis-driven yield analysis in 2009 and its acquisition of LogicVision, also in 2009.
Pateras cited two customers who have successfully applied Mentor’s test products. First, ASIC design company Open-Silicon has used the Tessent TestKompress product with Cell-Aware Test to improve test quality of SoC designs. By using the Tessent TestKompress product, Open-Silicon succeeded in detecting and resolving defects previously undetected using traditional techniques. Open-Silicon also has deployed the Tessent MemoryBIST product for at-speed testing, diagnosis, and repair of embedded memories.
Cell-Aware Test, Pateras said, is a transistor-level test methodology that improves the detection of defects internal to standard cells by targeting specific shorts, opens, and transistor defects internal to each standard cell. He said that the technique will become increasingly important for testing FinFETs, whose critical dimensions are significantly smaller than node size. Cell-Aware ATPG, he said, allows modeling of complex transistor-level defect behaviors.
In addition, Pateras said, Renesas Electronics is using Mentor’s Tessent Hybrid TestKompress/LogicBIST solution to address safety-critical test requirements defined by the ISO 26262 functional safety standard for road vehicles. In particular, Tessent Hybrid TestKompress/LogicBIST supports Power-On Self-Test. The hybrid technique requires significantly less test logic to provide a complete solution, including both high-compression scan test for low defects per million (DPM) and BIST. Mentor’s hybrid test capability is suitable for high-reliability applications in the automotive and other industries.
The Tessent Hybrid TestKompress/LogicBIST solution delivers in-the-field system self-test complemented by compressed ATPG to achieve the highest test quality, even where the tester memory and interface are limited, such as during burn-in test. The solution generates LBIST logic integrated with embedded compression logic and automatically creates targeted top-up patterns compressed by 100x or more to complement the LBIST pseudorandom patterns. The hybrid solution can reduce production test time and cost while delivering low DPM and an in-system test capability.
Building on Boundary Scan
Also highlighted at ITC was the IEEE P1687 proposed IJTAG standard, where semiconductor design and test meet board and system test. Pateras said the challenge addressed by IJTAG is IP diversity, providing the analogy of each IP block within a chip speaking a different natural language; IJTAG establishes standardized communications interfaces to support faster integration, test, and debug. Relevant news at ITC was the announcement of full interoperability between Mentor’s Tessent IJTAG chip-level IP integration product and ASSET InterTech’s ScanWorks platform for embedded instruments.
As a result, Pateras said, ASSET tools can make use of Mentor’s Instrument Connection Language (ICL) and Procedural Description Language (PDL) files to support board- and system-level test generation and validation. The Tessent IJTAG tool reads ICL and PDL code delivered with third-party IP blocks and verifies that it is IJTAG-compliant. It then generates a logic network and associated ICL to integrate all the IP blocks in a design and processes the PDL for each IP to create composite chip-level PDL. The ScanWorks product then reads chip-level ICL and PDL for use in chip debug and retargets the PDL to a board- or system-level interface.
On the ITC exhibit floor, ASSET highlighted its collaboration with Mentor. ASSET also demonstrated an IJTAG-based test of a Cisco board containing an SoC produced by STMicroelectronics and designed using Synopsys DFTMAX technology. ASSET president and CEO Glenn Woppman said IJTAG has come of age with ratification of the standard expected in Q1 2014. He described the IJTAG ecosystem as consisting of ASSET (a debug tool provider) as well as EDA suppliers (such as Mentor and Synopsys), system integrators (like Cisco), and IC providers (like STMicroelectronics).
In related news at ITC, GOEPEL electronic introduced an Automatic Application Program Generator (AAPG) for design validation and test of FPGA-integrated high-speed I/O based on the ChipVORX technology. Heiko Ehrenberg, technology officer for ESA for GOEPEL electronics in the United States, said FPGA-based board designs often are difficult to test by traditional means because of a lack of physical access. But with the new AAPG, users can evaluate transmission-channel quality by utilizing bit error rate tests and viewing a dynamic eye diagram to support design validation.
In addition, JTAG Technologies showcased several JTAG Live products as well as new systems upgrades at ITC. With JTAG Live CoreCommander, for example, engineers now can activate the on-chip debug modes of a range of popular cores to affect kernel-centric testing. CoreCommander for FPGAs is a generic solution based on VHDL code that allows engineers to bridge from the standard JTAG test and programming port to proprietary IP cores and harness them for test purposes. A version is available for FPGAs.
Making Use of Test Data
The semiconductor test process results in the generation of much data. Speaking at ITC, Craig Nishizaki, director of ATE development at NVIDIA, described the rollout by NVIDIA’s silicon operations department of OptimalTest (OT) tools at subcontractors throughout Asia. “We use the tools to improve wafer-sort yields and to leverage test data to improve manufacturing yields,” he said.
As a fabless company, he said, NVIDIA must manage the manufacture and test of the chips that support the markets in which it participates. Test and product engineers, he said, had concluded that the company’s existing yield solutions had become less effective in improving yields and quality—test data was spread across multiple tools, it had become tedious to combine and analyze data from different operations, and there was no easy way to use data from one operation (wafer acceptance test, for example) at another (such as final or functional test). The company wanted a convenient way to implement yield monitoring and improvement, yield analysis, and customer return analysis (RMA).
Using WAT and CP analysis, he said, the engineers can closely monitor WAT parameters and determine how they affect yields. “We can see the effects of test hardware like probe cards and get information in minutes instead of hours or days. We can discover probe sensitivity before it’s too late.”
The use of the OT tools poses no impact on test time, he said, adding, “We feel the OT tools are extremely powerful.” He said NVIDIA has established an ongoing collaboration with OT, using virtual test (involving the creation of custom parameters and combinations to gage quality of part) and data feed forward (involving a preventive signature profile with escape prevention rules and a real-time bin switching infrastructure to create a safety net to avoid future RMAs).
Looking to the Future
As engineers contend with today’s test challenges, they are looking to the future in events like Test Vision 2020, held in conjunction with SEMICON West, and the 3-D Test Workshop, held in conjunction with ITC. At ITC, FormFactor featured its 40-µm grid-array pitch contactor technology for direct testing of through-silicon vias (TSVs) as well as grid-array microbumps or copper pillars for 2.5-D/3-D IC integration. Mike Slessor, former CEO of MicroProbe and now head of FormFactor’s MicroProbe Business Unit, said the proprietary contactor technology is being evaluated by memory semiconductor manufacturers in their TSV development programs. At the 3-D Test Workshop, FormFactor presented a paper on direct probing of microbumps in conjunction with Elpida Memory.
Test Vision 2020 provided a broad look at emerging test challenges ranging from Cell-Aware Test to the development of a virtual engineering assistant. A concluding panel tried to predict what test will be like in 2023. Among the predictions: With a trillion transistors in a package, the known-good die will be a thing of the past. We’ll settle for pretty good die. We will require built-in redundancy along with continuous dynamic self-test and repair leading to graceful degradation. Perhaps events in 2014 will provide a clearer picture of what this future will look like.
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