ATE Board, General, and Semiconductor

Designing a load board or circuit board for IC testing sounds like a routine task that involves a few basic requirements and some common-sense approaches. But it’s not always that simple. With new technologies and increasingly complex design requirements, there now are more issues than ever to consider in optimizing a load board.

Some factors, like substrate material selection, are fundamental. Others differ with specific designs, including board layout; component placement; the number, placement, and size of vias; load board grounding; and pad sizes. These factors all help minimize crosstalk. Many times, modeling ties all of these components together to determine if the electrical performance will be met before the board is fabricated.

Taken literally, embedded test is just that: test capabilities that exist wholly embedded within a system. Power-on self-test is an example as is a built-in performance-monitoring feature programmed to do something if an exception occurs. Many microprocessors and microcontrollers either include or work with a watchdog timer that performs a system reset if the watchdog times out. Depending on the nature of the overall application, several performance-related metrics could be periodically checked before each reinitialization of the timer.

A leading government contractor of electrical distribution and control systems retained G Systems to deliver a complete software upgrade for obsfolete 30/60-kW generator test stands.

Semiconductor manufacturers continue to look for ways to reduce the cost of test for producing mixed-signal SOC and SIP devices. Parallel test strategies, known as multisite test, implemented on ATE have grown from two sites a few years ago to eight or more sites today.

Looking into the future, continued increase in site count will encounter some significant challenges. For example, the amount of device interface board space available to hold the handler device contactors and the applications circuitry for mixed-signal devices is limited.

Of course, cost, size, and switching speed also are important factors. If they weren’t, big, expensive relays rated for very high current might be the best choice for most DC and low-frequency switches. Large contacts have lower resistance so they would seem to have less effect on signal integrity.

The semiconductor ecosystem spans the design, test, and manufacturing environments. As a part of this ecosystem, ATE can do much more than test and bin devices. It can be an integral part of an overall process to identify design defects, improve yield, and reduce defect escapes. A well-designed system can continuously reduce manufacturing test costs and reduce the time-to-revenue for a new product.

As the developed world attempts to move to a more green lifestyle, electric vehicles clearly are becoming a growing part of the automotive scene. They promise low or no emissions and conceivably low cost of fuel from the power grid, yet they will deliver us safely to and from work and shopping. But their design is a paradigm shift for the auto industry—new test and validation challenges to the industry as the electronics content of the vehicles grows.

Scan diagnosis is an established method for identifying and locating semiconductor defects on devices that fail manufacturing test and on field returns. Effectively selecting the right devices for failure analysis is a challenge. To address this challenge, some semiconductor manufacturers have incorporated scan diagnosis into the yield analysis process.

As PCB component density has increased, many more new designs are based on boundary scan-enabled parts because physical access has virtually disappeared. Today, complex ICs encompass several forms of built-in test intelligence, and the boundary scan (JTAG) test port has become a popular means of access.

Metaphorically speaking, a switching system is the glue that connects a UUT to a system’s test equipment. But all too often, it gets overlooked in the overall system design process. In reality, switching hardware may involve more potential solutions and compromises than any other part of the test setup.

For years, the defense and military communities have been faced with increasing pressure to incorporate advanced Prognostic Health Management (PHM) solutions into high-value turbine jet engines. Beginning around 1994 and coinciding with the launch of the Joint Strike Fighter program, interest in PHM development has escalated rapidly within the U.S. Navy and U.S. Air Force as a targeted, critical technology for improving the affordability of advanced aircraft systems through reduced maintenance costs and improved useful-life survivability.

Rising fuel prices over the past few years and the urgent need to reduce the carbon footprint related to transportation have triggered an increased demand for fuel-efficient hybrid electric vehicles (HEVs). These vehicles provide greater efficiencies than their conventional counterparts and offer similar, if not improved, performance.

Switching probably is the most overlooked and undervalued part of a test system design. Great attention is spent selecting the measurement and stimulus instruments. But more often than not, the signal switching solution does not complement the instruments. It doesn’t matter how accurate the instruments are if the signals pass through a poor switch to get to them.

When a global provider of air traffic, navigation, and landing system solutions began implementing its next-generation system, limitations of an existing test and debug methodology directly impacted the bottom line. But adding boundary scan testability to an existing product greatly reduced test and debug time.

As the prime contractor for the U.S. Navy’s Trident D5 missile guidance system, Draper Laboratory oversees the MARK 6 MOD 1 development team of more than 700 engineers from Draper and its major subcontractors as it modernizes the missile’s MARK 6 inertial guidance system. The goal is to extend the life of the MARK 6 to 2042 while lowering the Navy’s future maintenance and support costs and providing a flexible architecture to support new missions and upgrades.

Testing transceiver and converter interfaces requires orthogonal in-phase and quadrature (IQ) analog signals; that is, the phase relationship of the two must be very close to a 90-degree phase offset, and their relative amplitudes must be balanced. Achieving this with older ATE systems requires calibration circuits on the DUT board. Relays are used to bypass the device site and route stimulus IQ signals into digitizers.

Draper Laboratory has been the design agent for all U.S. Navy strategic guidance systems since Polaris and for the U.S. Air Force Peacekeeper missile guidance system. In addition, Draper has designed or helped develop radiation-hard, highly reliable inertial sensors for all of the U.S. strategic systems.

LXI and the IEEE 1588 Precision Timing Protocol have many advantages that coordinate the timing of instrument systems with accuracy into the nanosecond range.^1,2 But as powerful as this arrangement is, there are applications where it is not appropriate, particularly in systems distributed by large distances from thousands of feet to thousands of miles.

High-speed interfaces for the computer, consumer, and communications markets have moved dramatically forward, increasing from a few hundred megabits per second to much faster gigabit speeds, in some cases up to 10 and 12 Gb/s. These rapid improvements in performance have created significant test challenges, requiring major changes in test methodologies and, in many cases, true cross-domain test approaches.

Since its adoption in 1990, IEEE 1149.1 has enjoyed great popularity. The standard was built on the work of an industry organization, the Joint Test Action Group (JTAG), formed in the mid-1980s to provide a pins-out view from one IC pad to another to help test engineers locate and discover faulty PCBs.

Don’t look for atomic-powered cable/harness testers. The present crop of testers isn’t quite that revolutionary, but they do incrementally improve upon those available a couple of years ago by increasing measurement range or adding capabilities and features such as an integral LRC bridge or fiber-optic testing.

Because virtually every test application has some aspect that is unique, there is no such thing as a standard test setup. Instead, the test system integrator must determine the combination of instruments, test fixtures, and switching that best addresses the requirements.

Saying that advanced ICs are complex is an understatement. The seemingly endless progression to smaller geometries, the ever-increasing integration between analog and digital blocks, and the diminishing voltage supply are just some of the factors contributing to the complexity of today’s chips. Add to this the need for energy efficiency in portable and wireless IC designs, and the level of concern over power use and control during production test that is on the rise.

Since the first transistors went into production almost six decades ago, semiconductor manufacturers have looked for ways to reduce test time and manufacturing costs. As the industry has grown from transistors and diodes to integrated circuits and now complex SOC and SIP devices, the constant need to reduce cost of test continues with even more intensity.

Circuit board test, like any step in the PCB assembly process, benefits from lean manufacturing practices that continually improve process steps. If lean manufacturing principles were applied to circuit board test, what would a lean test strategy and test platform look like? A viable option is an efficient implementation of lean board test that uses an open platform board test (OPBT) architecture.

Memory device markets are more uncertain today than perhaps they have been in their entire history. In manufacturing, uncertainty can be addressed by equipment that can scale to needs and is flexible to adapt to changes in products. In the memory test business, uncertainty can take the form of changing pin-counts; test strategies such as wafer sort, known good die (KGD), and core final test; and even device technology including DRAM, flash, and multichip packages (MCPs).

Developing an automated production test solution for current and next-generation complex RF SIP/SOC devices is an increasingly difficult task. Both the test program and the device interface board (DIB) that mounts between the ATE system and the device handler are substantially more challenging design efforts for 3/4G devices.

Electromechanical relays for testing products ranging from automotive engines to thermocouples are readily available, low-cost devices you can use to route signals originating from almost anywhere. It is no wonder that they have become ubiquitous in the automated test market. But despite industry adoption, electromechanical relays are relatively slow at hundreds of channels per second and have limited lifetime, which makes them less suited for some applications.

The concept of virtual instrumentation is more than 30 years old, and its tenets are as true today as they were at its inception. Test functionality is defined by the user in software, as opposed to instrument functionality fixed by the equipment vendor using application-specific modular hardware.

As test engineers continue to maximize production efficiencies, they need to become more aware of ways to decrease test time and the cost of test. Evaluating the speed vs. accuracy trade-offs involved in making multichannel measurements is essential when selecting the right type of DMM and switching hardware.