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Expanded Role for JTAG DFT
by Dave Bonnett, ASSET InterTech
Don’t let poor DFT haunt your product for its entire life cycle.
In recent years, boundary scan has transformed itself. JTAG started more than a
decade ago as a simple structural interconnect test technology. It now is a
foundational embedded infrastructure capable of hosting a varied collection of
structural and functional test technologies, diagnostics, and in-system
programming techniques targeted at the chip, board, and system levels.
Along with the expanded role for JTAG, the expectations for boundary scan as
well as its critical importance in many test and manufacturing strategies have
increased accordingly. At this stage in JTAG’s development, fulfilling these
expectations depends as much on how well or how poorly the JTAG infrastructure
is designed into chips, circuit boards, and systems as it does on the innate
capabilities of the boundary scan technology itself.
Getting Started With JTAG DFT
A typical boundary scan infrastructure comprises the scan cells designed into
components:
• Test access port (TAP) on each device
• JTAG registers within devices
• Connections between devices, referred to as the scan path
• JTAG signals on the circuit board including test clock (TCK), test mode (TMS),
test data in (TDI), test data out (TDO), and the optional test reset (TRST)
• Any multidrop devices that manage access to scan path
• Electrical interface to any tools that may be used as a user-friendly way of
interacting with the embedded capabilities of boundary scan (Figure 1).
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Figure 1. JTAG Infrastructure Including Embedded Cells, JTAG
Signals, and a Scan Path |
In general, after as many JTAG devices as possible have been specified, the scan
paths on the board must be thoughtfully designed. First, access to the TAP
should be provided at the primary contact point on the board such as an edge or
a plug-and-socket connector. In addition, skew in the JTAG signals should be
eliminated, or faulty results may occur.
To reduce noise from backplane signals and signal skew on the scan path, buffer
devices should be placed on the PCB at the TAP entry and exit points. Moreover,
the TCK and TMS signals must be terminated to avoid reflections.
Just because a component may not have embedded boundary scan resources on-chip
doesn’t mean that it can’t be included in JTAG tests. Certain DFT considerations
should be followed to maximize the JTAG test coverage of non-boundary scan
devices and minimize their impact on boundary scan testing.
First, the signal I/O pins on non-boundary scan devices must be characterized.
Some boundary scan tool vendors support device models that include this
information, relieving design engineers from the task of manually characterizing
non-boundary scan devices. To avoid unsafe bus contention conditions, the
automatic test-pattern generation tool must be aware of whether non-boundary
scan pins connected to a boundary scan net are inputs, outputs, tri-state
outputs, or bidirectional.
Other types of devices, such as series resistors and line drivers, can be set in
the transparency mode where the logic values on the inputs are passed to the
outputs with no change. If these devices can be set in this bypass mode by the
boundary scan test system, they, too, can be included in a boundary scan test.
Several other design practices will extend JTAG test coverage to non-boundary
scan devices. First, if possible, boundary scan pins or the primary connection
to the board should have access to the non-boundary scan pins. Second, where
feasible, direct access to key control signals on non-boundary scan devices must
be provided so the devices can be configured to the correct state during test
application. If direct control is not possible, indirect control should be
provided from an unused boundary scan cell. Third, any free-running clock or
watchdog timers should be controllable by boundary scan cells.
Onboard Programming With JTAG
Increasingly, the chip-level access of JTAG is applied to the programming of
complex programmable logic devices (CPLDs), field programmable gate arrays
(FPGAs), and flash memories. Certain design practices ensure an efficient
programming process.
First, the programmable devices must be on the scan path to be accessed and
programmed by a boundary scan test system. This also applies to logic devices
like FPGAs that use many methods of loading configuration data at power up.
Furthermore, while a logic device is being programmed, adjacent devices should
be placed in a safe state with either the high-impedance (HIGHZ) mode or the
fixed-output (CLAMP) mode.
In the case of flash memory, an adjacent device such as an application-specific
integrated circuit (ASIC) with embedded boundary scan is connected to the
address, data, and control pins on the flash memory (Figure 2). Although
programming can be accomplished with this sort of layout, changing the values of
the flash device’s write enable (WE) pin through the boundary scan register
would be very time-consuming.
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Figure 2. Programming Flash Memory With JTAG |
The programming process can be accomplished much faster by connecting all of the
flash programming control signals including WE and ready/busy (RDY/BSY) directly
to the discrete I/O pins on the boundary scan test system’s interface pod
through the board’s edge connector (Figure 3). With this implementation, the
boundary scan ASIC’s EXTEST mode can be used to program the flash memory. Before
programming begins, all other devices on the boundary scan chain must be placed
in the CLAMP or HIGHZ mode, and all output pins should be set to safe values.
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Figure 3. Using JTAG’s EXTEST to Program Flash Memory |
If the capability to partition the scan path leading to programmable devices can
be designed-in, the programming process can be accelerated. For example,
programming flash devices is affected by:
• The frequency of the TCK on the boundary scan path.
• The total length of the boundary scan register that makes up the path.
• Whether the board is configured with direct access to the WE and RDY/BSY pins
on the flash device.
• Whether the VPP pin can be controlled by the JTAG test system.
The TCK speed on the boundary scan chain is limited to the slowest device on the
chain. For instance, one 5-MHz boundary scan device on the chain limits the
programming speed to 5 MHz.
Fortunately, boundary scan linkers or bridge devices can be deployed to
partition a scan path, temporarily excluding slower devices while another device
on the primary scan path is being programmed. Designing-in the capability to
partition and reconfigure scan paths also comes in handy when boundary scan is
involved with related test techniques such as functional microprocessor
emulation test.
System-Level JTAG DFT
Applying boundary scan technology across an entire system containing multiple
circuit boards and subassemblies can have great benefit over the life of the
product. Once again, careful planning and well-thought-out design strategies are
critical to the eventual success of a system-level boundary scan deployment.
One example of the benefits of system-level boundary scan is its support for
functional tests carried out in environmental test chambers. Highly accelerated
life testing (HALT) or other functional tests often validate designs. If
environmentally stressing the system reveals a malfunction, applying
system-level JTAG diagnostics while the system still is in the environmental
chamber can identify, in a matter of minutes, whether structural faults are the
source of the functional problem. And boundary scan can isolate the possible
fault down to the net- or pin-level.
Most embedded system-level boundary scan deployments will be based on a
hierarchical multidrop architecture (Figure 4). In such a scheme, a boundary
scan gateway device interfaces each elemental unit to the system’s boundary scan
maintenance bus.
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Figure 4. A Hierarchical Multidrop Architecture for System-Level
JTAG Test |
The multidrop architecture allows all boundary scan signals to be routed to all
units in the system. Each circuit board or assembly with an addressable JTAG
gateway device can recognize the boundary scan information intended for it. This
information configures the local scan paths for the boundary scan tests or
programming operations to follow.
Advanced Boundary Scan Applications
In many more instances these days, boundary scan’s embedded infrastructure has
been adopted by related test technologies. For example, microprocessor emulation
testing historically has been a technique for microprocessor code debug and
functional design validation. But because it takes advantage of the chip- and
board-level access provided by boundary scan, processor emulation testing can be
thought of as complementary to JTAG.
With systems such as ASSET’s Extended JTAG Coverage, boundary scan can validate
the structural integrity of systems and PCBs, and emulation tests the
functionality of various devices and subsystems. Combining these two methods
gives engineers structural and functional test coverage on the same test
platform, and this can simplify the overall test process, increasing
productivity.
To capitalize on the strengths of both JTAG and emulation testing, several
design practices should be followed. First, carefully plan the boundary scan TAP
interface on a circuit board so that access to the CPU and the entire scan path
is provided. Some emulation tools do not tolerate other JTAG devices on the scan
path during emulation testing. If so, a method for targeting only the CPU during
emulation testing will be needed.
In addition, most emulation tools do not support scan-path gateway or management
devices. As a result, these tools cannot manage the scan path during emulation
tests. Multiplexers that can be controlled by non-boundary scan signals can be
implemented instead of JTAG gateway devices. Ultimately, it is better to perform
structural JTAG tests first and then apply emulation-based functional tests
after the structural integrity of the board has been verified.
Another new technology that rides on top of embedded boundary scan is the IEEE
1149.6 Boundary Scan Standard for Advanced Digital Networks. Unlike the original
boundary scan IEEE 1149.1 standard that defines a static DC test technology,
1149.6 specifies a test methodology for chip-level interconnects that are
dynamically AC coupled or feature differential signaling.
Prior to 1149.6, the static DC nature of 1149.1 prevented it from testing many
of today’s increasingly popular high-speed buses. High-speed fiber-optic
switching equipment, for example, already features hundreds, if not thousands,
of these high-speed serial links.
Following a few guidelines during design will help implement 1149.6 tests later.
Begin by reading and understanding the description in 1149.6 of possible
implementations of AC coupling on high-speed IO signals. Since special 1149.6
cells must be designed into semiconductor devices to support 1149.6 testing
techniques, as many 1149.6-compatible devices as possible should be specified
for a given design. More and more 1149.6-compliant devices are being introduced
all the time, but encouraging semiconductor vendors will certainly accelerate
the pace.
Because of the newness of 1149.6, there sometimes will be instances when a
1149.6-compliant device will be interconnected through a high-speed AC-coupled
signal to a device that is not 1149.6 compliant. When this happens, all of the
1149.6 fault coverage will not be achievable, but 1149.1 boundary scan tests
still can be applied. A fully functional 1149.1/1149.6 boundary scan test system
such as ScanWorks for High-Speed Buses will be able to take this into account.
The boundary scan tool should be able to support the following combinations:
• IEEE 1149.6 to IEEE 1149.6
• IEEE 1149.6 to IEEE 1149.1
• IEEE 1149.1 to IEEE 1149.6
• AC coupled IEEE 1149.1 to IEEE 1149.1
Design Automation Tools for JTAG DFT
Given the critical importance of boundary scan DFT, design automation tools for
JTAG finally are catching up with the needs of the industry. Similar to
traditional EDA tools, DFT automation tools give design engineers access to a
level of boundary scan expertise. Most companies would prefer that their design
engineers focus on leading-edge design techniques rather than DFT.
Early in the design process, a JTAG DFT tool could be a valuable asset to
designers because it could prompt engineers with queries to ensure that proven
JTAG design principals have been followed. The next level in automating JTAG DFT
and ensuring a high level of quality test coverage would be to analyze completed
schematics to ascertain whether the JTAG infrastructure has been implemented
properly and alert designers to alternative design structures that offer greater
JTAG test coverage.
Boundary scan testability can depend as much on adjacent non-boundary scan
devices as it does on 1149.1-compliant devices. An accurate DFT analysis is
based on the same information used to generate test patterns. Characterization
information or models for the boundary scan and non-boundary scan devices are
needed for testability reports and test pattern generation.
The JTAG testability report explains the design’s boundary scan test coverage.
In addition, this report could form the basis for recommendations concerning
changes or additions to the design that would increase the level of JTAG test
coverage.
The ROI on an EDA Tool for JTAG DFT
As with many types of technology tools, the worth of an EDA tool for JTAG DFT is
dictated by its return-on-investment (ROI). If the procurement cost of a tool
can be recouped in cost savings in a shorter period of time, the tool becomes
more valuable.
A JTAG DFT EDA tool generates cost savings by:
• Significantly reducing the time and effort it takes to produce a testability
study on a design. One equipment manufacturer predicted the average cost of a
testability study at approximately $7,200. Other estimates showed that a JTAG
DFT tool could reduce the time spent on a testability study from several weeks
to three days, yielding a cost of $2,000 for a testability analysis.
• Catching poor JTAG design practices and ensuring greater JTAG test coverage.
Improved JTAG test coverage generates cost savings on several fronts.
One round of savings comes from reducing the cost of ICT fixtures by decreasing
the number of test points and the complexity of the fixtures. The same OEM cited
earlier estimated a savings in this regard of approximately $9,000 for each
design. This figure resulted from cutting three days off board layout, reducing
fixture costs by 20%, and saving three days from the time normally devoted to
generating non-boundary scan tests. Other cost savings that result from greater
boundary scan coverage involve reducing the number of PCBs that require rework
and accelerating any rework by pinpointing production defects.
• Avoiding the costs that come about when a product introduction must be delayed
to revise an inadequate test strategy. Because of the short effective life of
many electronics products, any delay in a product’s introduction to the
marketplace can rapidly drive up costs.
For example, one formula accepted by industry experts projects that a one-day
delay in introducing a product expected to generate $200 million over an
18-month life would cost the company $1 million in lost revenues. For each
successive day of delay, the firm pays another $1 million in costs.
Cost-Saving
In a sense, vendors can choose between very expensive DFT or cost-saving DFT.
High costs stemming from poorly executed or inadequate DFT can haunt a product
for its entire life cycle. But, the opposite also is true. Tools now are
available that automate sound JTAG DFT practices. And with solid DFT upfront, a
product’s costs for design debug, manufacturing test, maintenance,
troubleshooting, and repair can drop significantly.
About the Author
Dave Bonnett is the technical marketing manager and co-founder of ASSET
InterTech. He holds a B.S.E.E. from Southern Methodist University and spent 21
years with Texas Instruments prior to founding ASSET in 1995. He served as vice
chair of the IEEE 1532 Working Group and has authored numerous articles and
conference papers on boundary scan test and in-system programming. ASSET
InterTech, 2201 N. Central Expressway, Suite 105, Richardson, TX 75080,
972-437-2800, e-mail: dbonnett@asset-intertech.com |